1. Field of the Invention
The present invention relates to a common voltage compensating circuit in a liquid crystal display device, and more particularly, to a common voltage compensating circuit for implementing high resolution and high frequency, and enhancing common voltage signal deviation due to RC delay between wirings formed on a liquid crystal panel in a large-sized narrow bezel type liquid crystal display device, and a liquid crystal display device including the same.
2. Description of the Related Art
With the development of various portable electronic devices such as mobile phone, notebook computer, or the like, the requirement for flat panel display devices applied to those portable electronic devices has been gradually increased. For those flat panel display devices, studies on Liquid Crystal Display (LCD), Plasma Display Panel (PDP), Field Emission Display (FED), Organic Light Emitting Diodes (OLEDs), and the like have been actively carried out, but at present liquid crystal display (LCD) devices are primarily used because of their mass production technology, effective driving method, and high-definition and large-sized screen.
The liquid crystal display device is a device for controlling optical transmittance through an electric field formed on a liquid crystal capacitor in response to a data voltage input thereto to display an image, which is comprised of a liquid crystal display panel for implementing an image, and a drive circuit for driving the liquid crystal display panel.
FIG. 1 is a view illustrating an example of a typical liquid crystal display device.
As illustrated in the drawing, a liquid crystal display device in the related art may include a liquid crystal display panel 10 for displaying an image, a gate driving unit 20 and a data driving unit 30 for driving the liquid crystal panel 10, and a common voltage compensating circuit 50 for supplying a common voltage (Vcom) to the liquid crystal panel 10.
The gate driving unit 20 is mounted at a side end of the liquid crystal display panel 10, and the data driving unit 30 for providing a data voltage in a direction perpendicular to the gate driving unit 20 is mounted and attached to a Flexible Printed Circuit Board (FPCB) 35.
Furthermore, a plurality of gate lines (GLs) and data lines (DLs) are crossed with each other to define pixel regions at an inner side of the liquid crystal display panel 10, and a thin-film transistor (T) and a liquid crystal capacitor (LC) are formed at each pixel region.
The gate driving unit 20 sequentially supplies a gate driving voltage to the gate lines (GLs) for each horizontal period (1H) according to a plurality of gate control signals applied from a timing controller (not shown) mounted on a main printed circuit board (PCB) 40.
The data driving unit 30 supplies a data voltage (Vdata) to the pixel region through all data lines (DLs) for each horizontal period (1H) in response to a data control signal applied from the timing controller.
The common voltage compensating circuit 50 is to minimize the variation of a common voltage on the liquid crystal display panel 10 by applying a compensating circuit using inverting amplification thereto. The common voltage compensating circuit 50 continuously receives a common voltage (Vcom) fed back from the liquid crystal panel display 10 and outputs a common voltage (Vcom) compensated according to a compensation ratio, thereby constantly controlling a voltage level according to the variation of the common voltage (Vcom) generated on the liquid crystal panel display 10. The common voltage (Vcom) outputted from the common voltage compensating circuit 50 is applied to a common line (CL) formed on the liquid crystal panel display 10. A common voltage supply line (BL) connected to the common line (CL) is formed at a side end of the liquid crystal display panel 10, and the common voltage compensating circuit 50 is connected to the common voltage supply line (BL) through the output line (OL) formed on the FPCB 35 to supply a common voltage (Vcom) to the common line (CL).
Here, the common line (CL) supplies a common voltage (Vcom) to a first electrode of the foregoing liquid crystal capacitor (LC), and the data line (DL) applies a data voltage (Vdata) to a second electrode of the liquid crystal capacitor (LC), thereby implementing an image through an electric field between the two electrodes.
On the other hand, the foregoing common line (CL) is disposed adjacent to the gate line (GL) and data line (DL), and when a voltage level applied to the two lines (GL, DL) is abruptly changed, it causes distortion to the common voltage (Vcom) applied to the common line (CL) due to a parasitic capacitance therebetween and the like. It is a main cause of cross talk. In order to solve the problem, the common voltage compensating circuit 50 is typically configured with a structure in which a common voltage (Vcom) applied to the liquid crystal panel display 10 is fed back to control a common voltage (Vcom) level being outputted by reflecting the voltage level variation.
To this end, a common voltage feedback line (FL) for which ends thereof are connected to each other adjacent to the common voltage supply line (BL) is further formed on the liquid crystal panel display 10, and the varied common voltage (Vcom) is transferred to the common voltage compensating circuit 50 through the input line (IL) formed on the FPCB 35.
Here, the common voltage compensating circuit 50 may include an OP amplifier (not shown) for controlling the fed-back common voltage (Vcom) according to a resistance ratio, and the common voltage compensating circuit 50 outputs a common voltage (Vcom) to the output line (OL) through an output terminal of the OP amplifier, and the common voltage (Vcom) is fed back through an inverting (−) input terminal of the OP amplifier connected to the input line (IL) to control the output common voltage (Vcom), thereby minimizing image quality degradation.
Such liquid crystal display devices are tending toward high resolution and high frequency, and narrow bezel type, and the studies thereof have been carried out in the form of gradually decreasing a width of the common line (CL) within the liquid crystal panel display 10, and decreasing a gap between the common line (CL) and gate line (GL) and data line (DL) in order to obtain a high transmittance.
However, the level of distortion of the common voltage (Vcom) is increased as increasing an area of the liquid crystal panel display 10 as well as decreasing a width of the common line (CL), and particularly, in case of the common lines (CLs) formed on the liquid crystal panel display 10, a voltage level difference between the applied common voltages (Vcoms) due to RC delay according to the location electrically connected to the common voltage compensating circuit 50 is further increased compared to the related art. In other words, a large deviation may occur between the common voltages (Vcoms) on a portion connected to the common voltage supply line (BL) and a portion opposite thereto even on one common line (CL).
Furthermore, referring to FIG. 2, in case of a large-sized liquid crystal panel 10, it may be divided into three regions (A1-A3) from the top to the bottom, and connected to the common voltage compensating circuit 50 at a side end thereof, and thus when the common voltage (Vcom) is applied thereto, common lines on the upper region (A1) adjacent to the common voltage compensating circuit 50 according to the RC delay of the common line causes a small signal delay, but other common lines on the lower region (A3) causes a large signal delay.
As a result, when a voltage compensation ratio of the common voltage (Vcom) is adjusted based on any one region (A1), it may cause a problem that the other regions (A2, A3) cannot be set to a normal voltage level of the common voltage (Vcom) due to the deviation. It may be a main cause of horizontal cross talk.